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This thesis presents a complete digital back-end implementation of a PN-dither least-mean-squares (LMS) background calibration scheme for a 12-bit, 500 MS/s pipeline analog-to-digital converter (ADC). The target converter, designed by a parallel analog project, comprises four 3-bit stages and a 4-bit final flash stage; its actual inter-stage gains depart substantially from their nominal values, re
